This answer record is part of the xilinx mig solution center xilinx answer 34243. Xilinx xapp496 creating wider memory interfaces using. Determining a root cause for a hardware issue can be a time consuming process. The ddr2 device, a mt47h64m16hr25e or equivalent, provides a 16bit bus and 64m locations. Memory interface generator mig on spartan 6 sp601 evaluation platform hello, i have a spartan 6 sp601 evaluation board. I have read documentation on how to generate the mig core no problem. Simple ddr3 interfacing on skoll using xilinx mig 7. I need to design a counter that can store upto 100 numbers in the ddr 2 ram and print them back. I have created a usbuart interface to communicate with the fpga and. The arbiter inside the mcb uses a time slot based arbitration mechanism to determine which of the one to six ports of the user interface curre. The axi spartan 6 fpga ddrx memory controller does not support qos.
What is traffic generator while using xilinx memory. As i undertstand it to drive multiple dcmplls from the one input clock theres needs to be one ibufg driving both they cant be placed in series nor parallel. Click on generation in the left pane to access the design flow options. When using a custom part, you must identify a base part, which matches your memory devices data width and memory. The xilinx mig solution center is available to address all questions related to mig. Mig spartan 6 mcb masking data with the user interface. For further details on specifying your memory device in the gui, see setting controller options in the spartan 6 fpga memory interface solutions user guide ug416. This part of the mig design assistant will guide you to information on performing reads to the user interface. Complete and uptodate documentation of the spartan6 family of fpgas is available on the xilinx website at to implement an mcb based memory interface, one of the two supported design tool flows must be followed. Except as stated herein, none of the design may be copied, reproduced, distributed, republished. Simple ddr3 interfacing on galatea using xilinx mig 6. Gmii mode using external ethernet phytypically used to connect to copper networks. Xilinx fpga training how to design a highspeed memory. If the specific memory device you are using is not listed, you can select create custom part to manually target many devices.
Spartan 6 fpga configurable logic block user guide. Ug086 xilinx memory interface generator mig, user guide. Mcb 10 ddr ddr2 ddr3 lpddr spartan 6 spartan 6 800 mbps1 800 mbps1 400 mbps1 400 mbps1. Click next, select component name and deselect axi4. This provides more than enough memory density and bandwidth for the majority of spartan 6 fpga applications. In the spartan6 fpga memory interface solutions user guide ug41 there is a constant reference to traffic generator.
Interfacing ddr3 and lpddr with the spartan6 hard memory. This trd is a x1 endpoint block for pci express v1. Memory interface generator mig standalone utility to customize memory cores spartan3a support. Xilinx xapp768c interfacing spartan3 devices with 166 mhz. So, i generated a mcb controller using the xilinx core generator using the mig tool, but now i am stuck. The purpose of this block is to determine which port currently has priority for accessing the memory device.
This course teaches hardware designers who are new to highspeed memory io to design a memory interface in xilinx fpgas. Using the ip generator in ise, i generated a mig wrapper and then i. I also want to use the spartan 6 s memory controller with the boards lpddr ram so im using the memory interface generator mig wizard. Xilinx xapp768c interfacing spartan3 devices with 166 mhz or. In the spartan6 fpga memory interface solutions user guide ug41. Whether you are starting a new design with mig or troubleshooting a problem, use the mig solution center to guide you to the right information. To use the memoory ddr2 ram on my board, i created a mig core using the coregen. Sdram interface for spartan 6 community forums xilinx. This section of the mig design assistant focuses on fpga input termination options for spartan 6 mcb designs. The xilinx memory interface generator configuration window will open. Simple ddr3 interfacing on skoll using xilinx mig 7 numato.
I generate mig core using core generator sing spartan 6 sp601 and ise. Xilinx xapp492 extending the spartan6 fpga connectivity trd. Xilinx is disclosing this user guide, ma nual, release note, andor specification the documentation to you solely for use in the development of designs to operate with xilinx. To be more precise, this would be on a spartan 6 with ddr3 ram. This article will demonstrate how to write to the ddr3 memory on galatea using simple verilog code and then read back the data. Whether you are starting a new design with mig or troubleshooting a problem, use the memory interface solution center to guide you to the right information. Whether you are starting a new design with mig or troubleshooting a problem, use the mig solution.
Supported by aldec no official xilinx support aldec. Below, you will find information related to your specific question. User interface a wrapper over native interface and the axi4 interface. It also generates ddr and ddr2 sdram interfaces for spartan 3 fpgas and ddr sdram interfaces for spartan 3e fpgas.
The miggenerated user design is the same as the example design except that it does not include a synthesizable test bench to generate various traffic data patterns to the memory controller. This answer record is a part of the xilinx mig solution center xilinx answer 34243. Support of traffic generator for axi4 slave interface of spartan 6 designs. Simple user interface abstracts away complexity of memory transactions. Whether you are starting a new design with mig or troubleshooting a problem, use the mig solution center. Xilinx ug388 spartan6 fpga memory controller user guide. This part of the mig design assistant will guide you to information on driving the user interface. Configuring the mig 7 series ip to use the ddr memory on. The spartan6 fpga mig ddr2ddr3 design can be generated with two output designs. The axi spartan 6 fpga ddrx memory controller does not support alow power interface. Simple lpddr interfacing on waxwing using xilinx mig 6. The fpga also contains an embedded controller and physical phy interface, 4bit, 8.
The tool take s inputs such as the memory interface type. Some systems require memory interface configurations that cannot be supported by a single mcb. Many modern applications use fpgas to implement complex system level building. However, i have referenced manuals ug388 and ug416, but i have not been. I came across some issues with the pin allocations. In the spartan 6 fpga memory interface solutions user guide ug41 there is a constant reference to traffic generator. Xilinx is disclosing this user guide, ma nual, release note, andor specification the documentation to you solely for use in the development of designs to operate with xilinx hardware devices. Xilinx answer 36291 mig, mpmc, spartan 6 mcb memory failures occur on initial configuration. Sp605 evaluation board mig ddr3 design the spartan 6 fpga contains dedicated memory controller blocks mcb for simplified dram interfaces, including up to four mcb cores in a single spartan 6 device. So we wont write any code or learn how ddr works in this tutorial.
Ddr3 sdram memory interface solution customizing and generating the core generation through graphical user interface the memory interface generator mig is a selfexplanatory wizard tool that can be invoked under the core generator software from xps. Select the spartan6 family, and then the target device, the package, and the speed grade for example, xc6slx16, cs324, 2 on the project options page. This section of the mig design assistant focuses on the miggenerated example design. It introduces designers to the basic concepts of highspeed memory io design, implementation, and debugging using spartan 6 and virtex 6 fpgas. Under the flow navigator, doubleclick on ip catalogue to add necessary ip cores. User manual and other tools for saturn is available at the product page.
User interface a wrapper over native memory interface and the axi4 interface. Interfacing micron ddr2 memories to xilinx spartan3aan. For more information on the user interface, refer to the xilinx memory interface generator mig 007 user guide ug067. Xilinx ug392 spartan6 fpga connectivity targeted reference. This document describes the spartan6 fpga memory controller block m cb.
Xilinx spartan3a user manual pdf download manualslib. I need to design a counter that can store upto 100 numbers in the ddr 2 ram and. The mig gui allows you to specify a number of preconfigured memory controllers for specific memory devices. Xilinx xapp492 extending the spartan6 fpga connectivity. As you have noticed, this requires at a minimum either ft256 8bit memory interface or csg324 package. Memory interface generator mig ddr2 design the spartan6 fpga contains dedicated memory controller blocks mcb for simplified dram interfaces, including up to four mcb cores in a single spartan6 device. Mig mapping problem of spartan 6 sp601 hello everybody. The spartan 6 mig design assistant walks you through the recommended design flow for mig spartan 6 fpga mcb designs while debugging commonly encountered issues, such as simulation issues, calibration failures, and data errors. The mig 6 ip core provides users with two interface options.
Additionally, you will learn about the tools available for highspeed memory interface design, implementation, and debugging. This section outlines general pin assignment guidelines for ddrddr2 sdram implementation. Sourcesynchronous data transmit data write function. The spartan6 fpga ddr2ddr3 mig design can be generated with two output designs. However, additional guidelines should be followed when targeting spartan 33e3a3a dsp devices. Spartan 3a3an starter kit board tm the ddr2 sdram interface has specific pin assignment ddr2 sdram termination network 1 of 2 and layout requirements to support the xilinx memory interface generator mig software. You might save yourself much time and trouble by using the spartan 6 mcb and the mig memory controller generator. The mcb supports memory densities up to 4 gb and data rates up to 800 mbs ddr2, ddr3 sdram, providing up to 12. Key challenges highspeed memory interfaces are challenging to design, due to factors such as. Xilinx spartan 6 fpgas has hard ddr memory controller builtin which. Spartan6 and ddr sdram memory your first ddr interfacing. Xilinx answer 38244 mig spartan 6 mcb why is rldram ii not supported. This release notes and known issues answer record is for the memory interface generator mig v3. Ddr, ddr2, ddr3, lpddr, and the specific memory part.
This part of the mig design assistant guidesyou to information on masking data with the user interface. Mar 08, 2018 the mig 6 ip core provides users with two options to interface with memory. When using a custom part, you must identify a base part, which matches your memory devices data width and memory depth. Mig mapping problem of spartan 6 sp601 community forums. The anvyl board has been tested for ddr2 operation at up to an 800mhz data rate. The memory interface generator mig solution center is available to address all questions related to the mig. This section of the mig design assistant focuses on the miggenerated user design for spartan6 fpga ddr3ddr2 designs. A traffic generator in this context is simply something that generates traffic on the memory interface. For more information regarding the axi interface, please see the spartan 6 fpga memory interface solutions user guide ug416, in particular, the edk flow details axi spartan 6. Network interface card referred to as the network path providing either.
Added more information on how to find the simulationonly debug signals. Search for mig 7 and double click on memory interface generator mig 7 series to customize. Virtex5 fpga xilinx memory interface generator mig user guide. Mar 09, 2018 the purpose of this article is to help readers understand how to use lpddr memory available on waxwing using xilinx mig 6 ip core easily.
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